Processing analog signals often involves the problem of how to achieve low energy consumption as the continuous current consumption of linearly operating active analog circuits, such as e.g. operational amplifiers, is considerable.
Basic methods are known from the prior art wherein the processing of signal samples may be performed by processing the signal by means of a switching transistor that only transfers charge impulses, instead of using structures that continuously consume current. Such methods are disclosed in patent documents FI 89838 (corresponding to EP 473,436 and U.S. Pat. No. 5,387,874), FI 931831 (corresponding to EP 621,550 and U.S. Pat. No. 5,497,116) and finnish patent document FI 101914.
Patent document FI 89838 discloses an integrating circuit wherein switches are used to control the storing in a sampling capacitor of charge samples taken from a signal voltage, and the discharging of charge samples from the sampling capacitor into an integrating capacitor. The circuit disclosed substantially consumes current only while charges are being transferred. The arrangement, however, has the drawback that it requires separate switch arrangements for the positive and negative cycles of the signal voltage as well as separate clock stages to control the switches, thus making the circuit complicated. Moreover, the use of separate circuit elements for the processing of the signal's negative and positive cycles may result in signal distortion caused by threshold voltages and component variation.
The drawbacks of the circuit described above can be avoided by using the arrangement disclosed in patent document FI 931831. To aid in understanding the operation of the present invention and its advantages over the prior art, the operation of the circuit arrangement disclosed in said document is described below in detail with reference to FIGS. 1 to 5.
FIG. 1 shows a signal processing circuit implemented with transistors T1 and T2, in which circuit the end result is a time-discrete integral of voltage (U.sub.S -U.sub.Ref). Transistors T1, T2 are N-type MOS transistors, or N-MOS transistors. Switches S.sub.21 to S.sub.30 in the circuit shown in FIG. 1 are controlled by clock signals 1 to 4. The clock signals 1 to 4 control the switches in four successive stages such that e.g. during clock stage 1 clock signal 1 sets the switches controlled by clock signal 1 into conductive state. Switches are below denoted using the letter S and indices such that the subscript refers to the switch number, which is running, and the superscript refers to the clock stages during which the switch is conductive. F or example, marking S.sub.21.sup.1,3 refers to switch 21 which is conductive during clock stages 1 and 3, controlled by clock signals 1 and 4. During the other clock stages 2 and 4 the switch is non-conductive. Similarly, a denotation of voltage provided with a superscript refers to the voltage appearing during the clock stage indicated by the superscript and a denotation of charge provided with a superscript refers to the charge appearing or transferred during the clock stage indicated by the superscript. Thus, U.sub.Ci.sup.2 refers to the voltage U of capacitance Ci during the end of clock stage 2. The clock pulses are so-called non-overlapping clock pulses, i.e. during a given stage only the switches intended to be closed during said stage are conductive, and the other switches are o pen.
The operation of the clock stages 1 to 4 in the circuit is described in detail in FIGS. 2 to 5, showing only those elements of the circuit of FIG. 1 that are essential from the point of view of the operation of the clock stage in question. The signs (i.e. polarities, e.g. positive or negative) of the signals and voltages are indicated relative to the ground potential.
FIG. 2 illustrates the operation during clock stage 1. Switches S.sub.21, S.sub.22, S.sub.23 and S.sub.24 are closed during clock stage 1 so that the charge-transferring capacitor C.sub.i, here also called sampling capacitor C.sub.i, is charged up to voltage U.sub.Ci.sup.1 : EQU U.sub.Ci.sup.1 =U.sub.S.sup.1 +U.sub.Ref +U.sub.th1 (1)
where U.sub.th1 is the threshold voltage of the gate-source voltage of transistor T1. When the gain of transistor T1 is large, the charge transferred to the sampling capacitor C.sub.i comes substantially from the circuit's supply voltage VDD and not from the signal voltage U.sub.S.
The operation during the subsequent clock stage 2 is illustrated in FIG. 3. During clock stage 2, switches S.sub.26, S.sub.27 and S.sub.28 are conductive (closed) so that the sampling capacitor C.sub.i supplies gate-source voltage to transistor T2, facilitating flow of current from the positive operating voltage VDD to the integrating capacitor C.sub.o. The current flow continues until the sampling capacitor C.sub.i has discharged down to the threshold voltage U.sub.th2 of the gate-source junction of transistor T2, at which point the current flow stops. So, charge is transferred from the sampling capacitor C.sub.i to the integrating capacitor C.sub.o until the voltage of capacitor C.sub.i has dropped to U.sub.th2. Thus, during clock stage 2, a charge is transferred from the charge-transferring capacitor C.sub.i to the integrating capacitor C.sub.o according to the equation: EQU .DELTA.Q.sup.2 =C.sub.i (U.sub.S +U.sub.Ref -U.sub.th1 -U.sub.th2) (2)
FIG. 4 illustrates the operation of the circuit during clock stage 3 when switches S.sub.21, S.sub.23, S.sub.24 and S.sub.25 are closed. The sampling capacitor C.sub.i is connected to the reference voltage U.sub.Ref via transistor T1 so that capacitor C.sub.i is charged up to voltage EQU U.sub.Ci.sup.3 =U.sub.Ref -U.sub.th1 (3)
FIG. 5 illustrates the operation of the circuit during the last clock stage 4 when switches S.sub.26, S.sub.29 and S.sub.30 are closed. The sampling capacitor C.sub.i supplies gate-source voltage to transistor T2 facilitating flow of current through the sampling capacitor C.sub.i from the integrating capacitor C.sub.o to the lower operating voltage VSS. The current flow continues until the sampling capacitor C.sub.i has discharged down to the threshold voltage U.sub.th2 of the gate-source junction of transistor T2. The negative charge transferred to the integrating capacitor C.sub.o is then EQU 66 Q.sup.4 =-C.sub.i (U.sub.Ref -U.sub.th1 -U.sub.th2) (4)
When the gain of transistor T2 is large, as it is in a good bipolar transistor, or near infinite, as it is in a field-effect transistor (e.g. MOS transistor), also the charge transferred at the charge transfer stages comes from the supply voltage (VDD, VSS) and has substantially that precise magnitude which is required to transfer the desired charge from the sampling capacitance C.sub.i to the integrating capacitance C.sub.o. The charge transferred during all clock stages 1 to 4 to the output of the circuit at the integrating capacitor C.sub.o, totals in the sum of equations (2) and (4), i.e. EQU 66 Q.sub.tot =C.sub.i (U.sub.s +U.sub.Ref -U.sub.ref)=C.sub.i U.sub.s (5)
Accordingly, during one cycle Tr of clock stages, i.e. during clock stages 1 to 4, the voltage of the integrating capacitor C.sub.o changes value according to equation (6): ##EQU1##
Thus, the circuit shown in FIG. 1 becomes a discrete-time, positive signal voltage integrating circuit the time integration weight coefficient of which is C.sub.i /C.sub.o. The sign of the integration can be changed to negative by interchanging the order of performance of the aforementioned clock stages 2 and 4, so that the operation according to clock stage 4 is performed after stage 1, and the operation according to clock stage 2 is performed after stage 3. Consequently, the signs of the abovementioned equations (2) and (4) and, thereby, the signs of equations (5) and (6), too, are inverted (positive becomes negative and negative becomes positive). This basic circuit may be varied according to the type of transistor used (NPN, PNP, N-MOS or P-MOS) and according to whether the circuit is to be implemented using one transistor instead of two (T1 and T2 above).
In the prior-art arrangement described above the circuit is substantially currentless after the charge transfer, and the dependence on threshold voltages and non-linearities of circuit elements is minimal. However, when realizing such a circuit using CMOS transistors, the circuit has three significant drawbacks. First, some of the switching transistors float along with the voltages processed, which in real-life implementations results in threshold voltage changes due to the so-called back-gate phenomenon. This shows as non-linearity in the operation of the circuit so that during sampling and transfer of samples a transistor may have different threshold voltages and, on the other hand, the threshold voltages may have differing values with signals of differing magnitudes. Typically, a transistor would float within one volt, approximately, whereby the threshold voltage could vary in the range of a few millivolts. Therefore, as regards the implementation of the method, it would be advantageous to minimize the variation of potential in the transistor.
Secondly, in the circuits of prior-art arrangements the way in which the transistor goes currentless is that the gate voltage drops to the threshold. This happens slowly, since the transistor's gate voltage VGS changes through the charging of capacitance C.sub.i, and said charging only occurs through channel resistance, which at the same time grows, approaching infinity. Thus the circuit may be slow and the growing channel resistance also causes noise.
The third drawback related to the prior-art arrangement described above is that the implementation of more than two (e.g. four) different clock signal stages complicates the circuit. Particularly in implementations integrated on silicon chips, the wiring of four clock signal stages requires a substantially greater area than the wiring of two clock stages even if the number of switches were not large. It is thus preferable to aim to minimize the number of clock signal stages required.
The drawbacks mention ed above can be partly avoided using an arrangement disclosed in patent document FI 101914. The operation of the circuit arrangement disclosed in said document is below described with the aid of FIGS. 6 to 8.
The operation of the circuit arrangement shown in FIG. 6 comprises two clock stages used to control switches S.sub.61 to S.sub.64 in the circuit. Clock signals 1 and 2 control the switches in two successive stages such that during clock stage 1 clock signal 1 sets the switches (S.sub.61, S.sub.63) controlled by clock signal 1 into conductive state. Similarly, during clock stage 2 clock signal 2 sets the switches (S.sub.62, S.sub.64) controlled by clock signal 2 into conductive state. To illustrate the operation of the circuit arrangement, FIGS. 7 and 8 separately show the elements relevant to the operation during both clock stages. The superscripts of the symbols representing switches and voltages are numerals indicating clock stages of the circuit arrangement as in the description of FIGS. 1 to 5.
The circuit arrangement according to FIG. 6 is below described using as an example a p-channel field-effect transistor T the threshold voltage of which is V.sub.T. The magnitude of the threshold voltage V.sub.T is typically of the order of -0.5 V. The current equations describing the operation of the p-channel FET in the region relevant to the operation of the circuit are as follows: EQU I.sub.D =1/2k(V.sub.GS -V.sub.T).sup.2 (7) EQU I.sub.D =kV.sub.DS (V.sub.GS -V.sub.T) (8)
A constant-current element I.sub.c used in the circuit produces a substantially constant current I.sub.c. However, the operation of the circuit is first examined without the constant-current element I.sub.c. During clock stage 1 (FIG. 7) the gate G of the transistor T is connected via switch S.sub.61.sup.1 to the signal voltage U.sub.S and a first electrode 23 of capacitance C.sub.i via switch S.sub.63.sup.1 to constant potential V.sub.r. A second electrode 24 of the charge-transferring capacitance C.sub.i is connected in a fixed manner to the source S of transistor T . Thus the capacitance C.sub.i is charged up to voltage EQU U.sub.Ci =U.sub.S -V.sub.T (9)
Let first U.sub.S.ltoreq.0 so that the absolute value of the voltage U.sub.Ci of t he charge-transferring capacitance is greater than the transistor's threshold voltage V.sub.T.
During clock stage 2 (FIG. 8) the integrating capacitance C.sub.o is connected in series with the charge-transferring capacitance C.sub.i through switch S.sub.62.sup.2 and at the same time the voltage U.sub.Ci of the charge-transferring capacitance C.sub.i is connected between the source S and gate G of transistor T through switch S.sub.64.sup.2. The circuit transfers charge from the supply voltage V.sub.DD until the voltage of C.sub.i has dropped to EQU U.sub.Ci.sup.2 =U.sub.T (10)
The charge transferred corresponds to the voltage change of the charge-transferring capacitance C.sub.i and its magnitude is EQU .DELTA.Q=U.sub.S.multidot.C.sub.i (11)
If U.sub.S &gt;0, the circuit will not operate as described above, because the voltage U.sub.Ci of the charge-transferring capacitance will during both clock stages be smaller than the threshold voltage V.sub.T of transistor T and current will not flow during either clock stage. Hence the constant-current element I.sub.c in the circuit. Below it is assumed that the current I.sub.c of the constant-current element is such that the circuit has time to reach balance during each clock stage. As the value of the current of transistor T decreases or increases to value I.sub.c the current flow to the charge-transferring capacitance C.sub.i stops, and from equations (7) and (8) we get the gate voltage corresponding to the cutoff, ##EQU2##
assuming that the transistor is operating in the linear, or triode, region. If the transistor were operating in the saturation, or pentode, region, the cutoff voltage would still be constant V.sub.T. In practice, the non-linearity according to equation (12) is caused by the fact that V.sub.DS varies to an extent comparable to the signal voltage. Since the value of the transistor-specific coefficient k is large, the distortion caused by the non-linear term is only a few millivolts at a signal voltage of 1 V so that below we can assume the current cutoff voltage to be V.sub.T. Let it be pointed out here that the transistor in FIGS. 6 to 8 is a PMOS-type transistor. With such a transistor, V.sub.T &lt;0 and the transistor is conductive when V.sub.GS &lt;V.sub.T.
During clock stage 1, the circuit is as shown in FIG. 7 so that the charge-transferring capacitance is charged up to the voltage EQU U.sub.C1.sup.1 =U.sub.S -V.sub.T (13)
If, prior to the clock stage, U.sub.C1 &gt;U.sub.S -V.sub.T, the constant-current element discharges the capacitance C.sub.i until U.sub.Ci reaches the value of equation (13) and during that time the current through transistor T is smaller than I.sub.c. During the clock stage, the current through transistor T settles to I.sub.c and is conducted to the constant-current element I.sub.c. The current flowing to capacitance C.sub.i is zero when the current of transistor T has stabilized to I.sub.c.
If, prior to the clock stage, U.sub.C1 &lt;U.sub.S -V.sub.T, the current of transistor T rises, exceeding I.sub.c, until the voltage U.sub.Ci of the charge-transferring capacitance reaches the value according to equation (7). After that, the current settles to I.sub.c which all flows to the constant-current element.
During clock stage 2 (FIG. 8) the integrating capacitance C.sub.o is connected in series with the charge-transferring capacitance C.sub.i, and the voltage U.sub.Ci of the charge-transferring capacitance, the magnitude of which is in accordance with equation (7), is connected as a control voltage for transistor T, between the gate G and source S of the transistor. If the voltage U.sub.Ci =U.sub.s -V.sub.T &lt;V.sub.T, transistor T is conducting more current than the value of I.sub.c to the constant-current element I.sub.c and capacitance C.sub.i until the voltage U.sub.Ci settles to V.sub.T and the current of transistor T settles to I.sub.c. If U.sub.Ci =U.sub.s -V.sub.T &gt;V.sub.T, the constant-current element discharges the charge-transferring capacitance C.sub.i until its voltage U.sub.Ci reaches the value V.sub.T. During that time the current of transistor T is momentarily smaller than I.sub.c, where it settles when the charge transfer from capacitance C.sub.i or to capacitance C.sub.i has stopped. The charge transferred through the charge-transferning capacitance C.sub.i is transferred to the integrating capacitance C.sub.o. The magnitude of this transferred charge is EQU .DELTA.Q=U.sub.s C.sub.i (14)
as in equation (11), which means the circuit cell described serves as an integrator.
The above-described circuit arrangement according to FIGS. 6 to 8 involves some problems:
In filter implementations, the problem is the sensitivity of the topology to parasitic capacitances. In analog-to-digital converter applications, problems are caused by the lossiness of the self-switched charge transfer (SSCT) integrator and by signal distortion. Below it is described with the aid of FIGS. 9 and 10 how the losses and signal distortion come about.
FIG. 9 shows a circuit corresponding to that in FIG. 7 at the first clock stage such that the drawing also shows the parasitic capacitance C.sub.p between the switches and the upper plate of the capacitor, which parasitic capacitance causes the lossiness of the integrator. In FIG. 10 the circuit is shown at the second clock stage.
At clock stage 1, FIG. 9, capacitor C.sub.p is charged up to the reference voltage V.sub.ref. At clock stage 2, FIG. 10, the parasitic capacitance C.sub.p is connected in parallel with integrator C.sub.o, causing the signal charge to be redistributed. The lossiness caused by the phenomenon is mathematically expressed as ##EQU3##
Minimization of the parasitic capacitance C.sub.p is limited by the maximum ON resistance allowed for the switches, because the parasitic capacitance of a switching transistor can only be reduced by applying a smaller W/L (width/length) ratio, and reducing the W/L ratio increases the channel resistance. Typically, the DC gain H.sub.o of the integrator is of the order of 10 to 20.
In the known SSCT topology, the gate potential of the active transistor is changed at the different clock stages of the circuit. Thus, there is a limit to the increase of the size of the transistor based on signal distortion caused by parasitic capacitances. However, the length of the transistor has to be sufficient in order to reduce the distortion caused by channel length modulation. These contrary design parameters determine the minimum distortion of the topology.